The method and system disclosed herein, in general, relates to storing data on a flash memory device. More particularly, the method and system disclosed herein relates to controlling the number of cells programmed to store data in a flash memory device and improving error recovery.
Flash memory devices use floating gates to store data. Flash memory devices comprise cells, for example, single level cells and multi-level cells. A single level cell (SLC) in a flash memory device holds one bit per cell. A multi-level cell (MLC) on a flash memory device holds multiple bits in each cell, which reduces the cost of flash based storage. As fabrication process geometries on flash memory devices shrink and the cells get smaller, charge in the floating gates gets smaller, and the cells are more prone to errors. Moreover, the endurance of each cell, that is, the number of times a cell can be programmed and erased, decreases with process geometries. Multi-level cell flash arrays are particularly susceptible to error due to shrinking geometries. Data retention in flash cells is also affected, for example, by read operations and write operations on neighboring cells, also referred to as read disturb and program disturb respectively.
Using flash memory devices, for example, solid state drives (SSD) to store data and replacing rotating magnetic storage devices, for example, hard disks, is gaining rapid traction due to the reduction in prices of multi-level cell flash memory devices. The data to be stored in the solid state drives requires mapping of logic storage blocks into flash blocks and pages. In most cases, logical addresses have more writes than others. Since the endurance of a page of a flash memory is limited, data from pages that are not frequently used are moved to accommodate pages that are more frequently used. This mechanism for prolonging the service life of solid state drives referred to as “wear leveling” creates write amplification, that is, it increases the number of writes on multi-level cell flash memory devices. Write amplification also occurs due to thresholds associated with read disturb, and from garbage collection to recover storage space from blocks of data that are deleted.
Numerous solutions have been proposed to increase the endurance of flash cells. There are two broad categories of solutions to improve flash memory performance in SSD storage. The first category involves circuit techniques that improve the cells in flash memory devices and associated read/write circuits. In addition, circuit techniques have been proposed to limit the effect of disturb to neighboring cells during a write operation of a block of data. The second category involves signal processing steps that improve data recovery and reduce the effect of cell interactions. Several solutions for program disturb have been proposed which alter the sequence of rows for block writes to flash memory devices. These solutions reformat the data to be stored to match the characteristics of flash memory device cells and arrays. For example, one solution proposes reduction in program disturb by reducing the number of cells that are not programmed and altering the distribution of programmed values. Another solution avoids program disturb by randomizing the data to a flash memory resulting in fewer cells that are not programmed, and changes in the distribution of programmed values when the data remains the same. However, these solutions do not help in applications that need faster programming. These solutions often fail to limit the number of write operations to fewer flash cells. Moreover, these solutions often fail to reduce the number of erase operations on the flash cells by performing erase operations on fewer flash cells. Furthermore, a number of these solutions operate on the original data block rather than reorganizing the data in the data block to enable faster programming. This raises a significant problem since with the probability of bit errors increasing with the shrinking of flash cell sizes, the number of bit fields required to accommodate error correction bits increases. Conventional solutions for improving flash memory performance often store the error correction bits in a separate page and region of the flash memory. However, these solutions are constrained by a predetermined number of bits set for error correction, thereby allowing correction of the same number of bit errors for all data, which does not allow the flexibility of changing the number of error correction bits in accordance with the data programmed in a page.
Hence, there is a long felt but unresolved need for a method and system that manages storage of one or more data blocks in a programmable data storage device by minimizing the number of cells that go through program erase cycles for each write, while minimizing the effect of program disturb. Moreover, there is a need for a method and a system that reduces the number of columns in the programmable data storage device that are to be written. Furthermore, there is a need for a method and system that improves the recovery of a number of bit errors. Furthermore, there is a need for a method and system that reconfigures the data programmed into a page for enabling a dynamic generation of a number of error correction bits for the page based on the reconfigured data, thereby allowing a flexible configuration of error correction bits and improved error correction.